Issue |
SHS Web Conf.
Volume 102, 2021
The 3rd ETLTC International Conference on Information and Communications Technology (ETLTC2021)
|
|
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Article Number | 04021 | |
Number of page(s) | 9 | |
Section | Applications in Computer Science | |
DOI | https://doi.org/10.1051/shsconf/202110204021 | |
Published online | 03 May 2021 |
A generator tool for Carry Look-ahead Adders (CLA)
University of Western Macedonia, Department of Electrical and Computer Engineering, Kozani, Greece
* e-mail: dziouzios@uowm.gr
** e-mail: dtsiktsiris@uowm.gr
*** e-mail: nbaras@uowm.gr
**** e-mail: bibi@uowm.gr
† e-mail: mdasygenis@uowm.gr
A carry look-ahead adder (CLA) is a digital circuit which is used widely used in any electronic computational device to improve speed calculation by reducing the time required to define carry bits. Despite the fact that CLA is used massively in modern digital systems, there is no online tool to automatically generate the HDL description. For this reason we developed a cloud based tool to automate the design of optimized CLA and provide custom testbenches to verify their correctness for singed and unsigned numbers. It is also can be used by the students to create and understand deeply the way CLA works.
© The Authors, published by EDP Sciences, 2021
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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